They are looking at trying to getting the last 10-40% of improvements in power usage and performance.
Need to change to different transistor architectures
Versions of today's FinFET transistors will be used down to the 5-nm node, said technologists from Synopsys and Samsung on the panel. Below a width of about 3.5 nm, FinFETs will hit a hard limit.
Designers will need to transition to a stack of probably three thin horizontal nanowires sometimes called nano-slabs, said Victor Moroz, a fellow and transistor expert at Synopsys. For its part, Samsung has announced plans to use a gate-all-around transistor for a 4-nm process that it aims to have in production by 2020.