TSMC's 2nm Process Scale-Up

TSMC's 2nm (N2) process will introduce nanosheet transistors (a form of Gate-All-Around or GAA architecture). It is on track for initial mass production in the second half of 2025, specifically targeting high-volume manufacturing (HVM) starting in late 2025. Risk production began in July 2024, with strong demand from clients like Apple, Nvidia, AMD, Intel, Qualcomm, and MediaTek driving rapid ramp-up. They have key facilities in Kaohsiung, Taiwan, are expanding, with nine new fabs planned for 2025 to support this.

Initial capacity in 2025 is projected at 40,000 wafers per month (wpm), scaling to 100,000 wpm in 2026 and doubling to 200,000 wpm by 2027, surpassing the capacity of its 3nm node by 2028. (post) Full utilization is expected by Q4 2025 due to high demand. Commercial adoption for end-user products (e.g., Apple's iPhone 18 chips) is slated for 2026-2027.

Samsung's Potential Lead with 2nm GAA

Samsung does not have a clear lead over TSMC in 2nm technology but they have started earlier in 2022 with GAA transistors starting at 3nm. Samsung's 2nm GAA process is progressing, with mass production targeted in months for the second half of 2025. They have challenges with lower yields (around 40%, compared to TSMC's reported 60%). They have recent improvements getting toward 50% and a focus on closing the gap over the the 3 years.

Competition is intensifying as we go beyond 2nm nodes to 1.8nm/18A, 1.6nm/A16 and 1.4nm/14A. TSMC leads in timelines for reliable HVM. Intel pushes aggressively with High-NA EUV (shipped in 2025) but faces delays. Samsung trails but could accelerate via partnerships.

Scaling Volumes and Projections

TSMC could have 200,000 wafers per month by 2025 of 2 nanometer node. A16 could reach 200,000 wafers per month or higher by 2030. Analysts forecast 15-30% annual capacity growth through 2030.

Samsung is targeting 50,000-100,000 wpm by 2028 for sub-2nm, focusing on mobile (Exynos) and AI chips. Projections show gradual increase if yields hit 60%+ by 2026.